1. Technical Field
The present invention relates to an encoding/decoding apparatus including an electronic device for accelerating encryption/decryption of digital data.
2. Description of the Related Art
Nowadays, as consequence of the increasing development in wireless communications, security and privacy of data transmission are great targets.
In fact, common used electronic equipments, such as smart cards, set-top boxes for digital television, mobile phones, PDA's are usually equipped with dedicated electronic blocks devoted to encrypt/decrypt digital messages and data which are transmitted or received by such equipments.
The electronic blocks are hardware devices integrated on a chip and called hardware accelerators by those skilled in the art.
In order to ensure a secure transmission of data and messages, the above indicated electronic blocks implement known encryption/decryption algorithms or block ciphers. For example, the most used block ciphers are the DES (Data Encryption Standard) and AES (Advanced Encryption Standard) algorithms. Particularly, as known by those skilled in the art, the AES algorithm implements Rijndael encoding and decoding in accordance with a standard proposed by the US National Institute of Standard and Technology (NIST).
Moreover, a AES block cipher can operate on blocks of data having a fixed length of 128 bits and is programmable for 128, 192 or 256 bit key lengths.
Because a message may be of any length, several modes of operation have been developed to allow block ciphers to guarantee confidentiality for messages having arbitrary length. Exemplary modes of operation are: the Electronic Codebook (ECB), the Cipher-Block Chaining (CBC), the Cipher Feedback (CFB), the Output Feedback (OFB), the Counter Mode (CTR) all that give privacy; the Cipher Block Chaining Message Authentication Code (CBC-MAC) mode which gives data integrity; the Counter with CBC-MAC (CCM) for achieving both data integrity and privacy.
For example, an encryption operation performed on a message according to the Counter Mode can be described with reference to FIG. 6. Particularly, in such FIG. 6, P1, P2, P3 and P4 indicate the input blocks of data composing the message to be encrypted. The Counter Mode employs AES block ciphers Ek and employs an Initialization Vector IV to kick off the operation. It should be observed that all AES block ciphers Ek encrypt data by employing the same key k.
The Counter Mode operates as follows: the vector IV, also named counter, is firstly encrypted by the first AES block; the result of such encryption is then put in XOR with the first input block P1 in order to produce the first encrypted block C1. Subsequently, vector IV is incremented and then encrypted by a further AES block Ek. The result of this further encryption is put in XOR with the second input block P2 in order to produce the second encrypted block C2. The same process is repeated up to the end of all the blocks composing the message.
Analogously, with reference to FIG. 7, an exemplary encryption operation performed on a message according to the CBC mode can be described. Particularly, P1, P2, P3 and P4 indicate the input blocks of data composing the message to be encrypted. The CBC Mode employs the AES block ciphers Ek and requires the Initialization Vector IV to kick off the operation.
The CBC Mode operates as follows: the first block of data P1 is put in XOR with the Initialization Vector IV; then the result of such operation is encrypted by the first AES block Ek; the result of such first encryption operation corresponds to the first encrypted block C1. Subsequently, the second block of data P2 is put in XOR with the produced first encrypted block C1; the result of such second XOR operation is then encrypted by a further AES block Ek in order to produce the second encrypted block C2. The same process is repeated up to the end of all the blocks composing the message to be encrypted.
Actually, hardware accelerators included, for example, in a digital decoder or in a mobile phone, are designed and manufactured to implement a limited number of standard modes of operation, as CBC mode and Counter Mode. In other words, such accelerators can not work implementing a mode of operation which is different from the prefixed ones.
Anyway, new modes of operation are proposed time after time for increasing security of encryption/decryption operations.
As consequence, each encryption/decryption operation based on a new mode must be executed (by software) by a main processor CPU (Central Processing Unit) provided in the digital decoder or in the mobile phone. This results in a reduction of the benefit of having the encryption/decryption operations managed by a separate hardware block.